I write hardware. From Verilog RTL on Zynq-7000 FPGAs to nationally ranked embedded prototypes — I think in gates, design in logic, and build things that run on silicon.
I don't just write Verilog — I push it through synthesis, implementation, and bitstream generation on real Zynq-7000 hardware. My Vivado workflows are documented and reproducible on GitHub.
NPTEL Elite + Silver — VLSI DesignTop 70 out of 2500+ teams at SPRINTATHON'25. Runner-up at InnovateX (₹15K prize). Best Innovation at HackTronix. I build fast, build right, and ship under pressure.
3 major hackathon wins in 20258.01 CGPA with relevant coursework in Digital Electronics, VLSI Design, Digital System Design, and Embedded Systems — backed by two NPTEL Elite + Silver certifications.
8.01 CGPA · GCE ErodeFrom FSMs in Verilog to ESP32 firmware with PID control and wireless protocols — I understand the full stack from gates to application. An embedded + VLSI hybrid that delivers complete systems.
GitHub-documented projectsPre-final year student with real silicon experience on Zedboard. Knows Vivado flows, understands timing constraints, and has shipped hardware projects — not just simulated them.
Zynq-7000 · Zedboard · 2026Exploring VLSI Physical Design flow with interest in RTL-to-GDS. Looking for research roles, internships, and collaborative environments where I can accelerate toward ASIC design.
Open to internships · 2025–26Developed GPIO-based digital logic experiments on the Zynq-7000 SoC using Zedboard. Implemented hardware interaction through board switches and LEDs via Vivado block design — from synthesis to bitstream generation. Created a fully documented, reproducible FPGA development workflow on GitHub for the community.
Designed and built a real-time Vehicle-to-Vehicle communication system using ESP-NOW wireless protocol. Features included dynamic message prioritization, automatic device pairing, multi-sensor fusion, and proximity-based safety alerts. Competed as a hardware prototype at national level — top 70 of 2500+ teams.
Systematic Verilog implementation series covering: ripple counters, synchronous counters, ALU arithmetic units, 4:1 multiplexers, LED state controllers, and Mealy/Moore FSM designs. Each module verified with testbenches and synthesised on FPGA. Foundation of practical RTL engineering skill.
Autonomous security vehicle with ESP32 at the core. Implements RFID-based access authorization, ultrasonic collision avoidance, autonomous patrol routing, and real-time intrusion notifications. Complete edge-intelligence system with no cloud dependency.
Built a competitive line follower with optimised sensor sampling rates and PID-style feedback control for smooth, high-speed tracking. Collaborated with a mechanical engineer to design and 3D-print custom wheels with improved traction geometry — first cross-disciplinary hardware collaboration.
Built a complete V2V communication hardware prototype from zero in under 24 hours. Competed against teams from top engineering institutions across India.
Recognised for the most innovative hardware prototype at one of Tamil Nadu's major hardware hackathons.
Top 70 rank nationally for Carmunicate — a real-time V2V communication device that competed across 2500+ teams.
Consistently shortlisted across multiple national-level hardware and innovation competitions — demonstrating consistent execution under pressure.